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This problem was solved be removing the termination resistors from the address and data lines.

TMS320C32 Silicon Errata

Rev 1.x Silicon (Document Revision 1.9)

Last Modified: 6/15/97

The following problems exist in the TMS320C32 silicon (all speeds included) known by TI as of the date given above. Each problem is described and an appropriate work around is presented. In addition, the revision in which the problem is fixed or will be fixed is included. Production release for the TMS320C32 is revision 1.2 silicon.

TI creates a new document revision when a new silicon bug is discovered. However, TI will NOT update previously edited files. For example, if you have silicon rev 2.2, you should take a look at the last document revision for 2.x silicon AND to the latest document revisions for newer silicon (i.e. 3.x, 4.x, ... document revisions) because unless specifically specified, old silicon has the bugs that have been discovered in newer silicon.

This document includes:

  • TMX Bug listing
    1. DMA priority bit swapping
    2. 8-bit data sign-extension
    3. Address pin glitches
    4. Data bus driven after HOLDA
    5. IOSTRB cycles may be missed after HOLDA
    6. TMX Parameter relaxation
  • TMS Bug listing
    1. Back-to-Back DMA transfers between two DMA channels to/from external memory
    2. Back-to-Back IOSTRB read and STRB0 or STRB1 read when these are not configured for 32-bit data and 32-bit wide memory
    3. Boot loading from and into the same memory space strobe with different memory widths
    4. IOSTRB access followed by a IOSTRB read back-to-back with and on-chip access
  • TMS Additional Functionality
    1. New Operand Combinations in 'C32 Parallel Instructions
  • TMS Data Sheet Corrections
    1. LOPOWER mode CLKIN to H1/H3 delay
    2. Interrupt setup time in IDLE2
    3. Corrected Reset Timing
    4. Address Bus Vol parameter relaxation
    5. CLKIN low min pulse width (parameter 3) relaxation - 50 MHz
    6. CLKIN low max pulse width (parameter 3) relaxation
    7. Note added in parameter 95, hold time for general purpose output to input after H1 high

TMX Bug listing

  1. DMA priority bits swapping error
    Problem fixed in silicon 1.1
    The bit 12 & 13 (DMA PRI) of the DMA control register has been swapped. See the table below for the functionality description:
     
       Correct mode |                                    | Rev 1.0 silicon mode
       Bit 13 - 12  |  Function Description              |  Bit 13 - 12
       -------------+------------------------------------+-----------------------
            0    0  |  CPU has higher priority over DMA  |       0    0
            0    1  |  CPU/DMA rotate priority           |       1    0
            1    0  |  Reserved                          |       0    1
            1    1  |  DMA has higher priority over CPU  |       1    1
       -------------+------------------------------------+-----------------------
     
  2. 8-Bit data sign-extended mode error
    Problem fixed in silicon 1.1
    The sign bit of the 8 bit data does not have enough power to drive the internal data low. The problem is occuring on upper 16 bit data bus and 8-bit positive sign-extended data only. The example below shows the problem:
    The memory configuration is 32-bit memory width and 8-bit data type.
    If the data is  012345678h in the 32 bit memory, in sign-extended mode, the 
    data will be as described in the following four situations:
     
                                      Correct       Error
                                     condition    condition
        Lowest LSBs  012345678h ---> 00000078h                   (no problem)
        2nd Byte     012345678h ---> 00000056h                   (no problem)
        3rd Byte     012345678h ---> 00000034h or FFFFFFB4h
        4th Byte     012345678h --->              FFFFFF92h      (always problem)
     
  3. 8-Bit data sign-extended mode error
    Problem fixed in silicon 1.2
    The sign bit of the 8 bit data does not have enough power to drive the internal data low. The problem is occuring on upper 16 bit data bus and 8-bit positive sign-extended data only. The example below shows the problem:
    The memory configuration is 32-bit memory width and 8-bit data type.
    If the data is  012345678h in the 32 bit memory, in sign-extended mode, the 
    data will be as described in the following four situations:
     
                                      Correct       Error
                                     condition    condition
        Lowest LSBs  012345678h ---> 00000078h                   (no problem)
        2nd Byte     012345678h ---> 00000056h                   (no problem)
        3rd Byte     012345678h ---> 00000034h or FFFFFFB4h
        4th Byte     012345678h --->              FFFFFF92h      (always problem)
     
  4. Address pin glitches
    Problem fixed in silicon 1.2
    Address pins generate glitches/pulses whenever the address changes on the rising edge of H1. This only occurs at the end of every external port write cycle:
     (write-write and write-read). 
           ^               ^
           |               |
         glitch          glitch
     

    This might impact the address ready timing.

  5. Address pin glitches
    Problem fixed in silicon 1.2
    The data bus does not tristate if HOLD is asserted just before a store to STRB0, STRB1 or IOSTRB cycle. In other words the data bus may be driven by the C32 even when the HOLDA signal is asserted.
  6. IOSTRB cycles may be missed after HOLDA
    Problem fixed in silicon 1.2
    If HOLD is asserted just before IOSTRB write cycle, the IOSTRB signal may never go low at the completion of HOLD condition.
  7. TMX Parameter relaxation
    Problem fixed in silicon 1.2
    The following relaxations were made for testing the TMX320C32 parts revision 1.1. These relaxations do not apply silicon revision 1.2.
    • 50MHz:
      • Data Bus setup time (parameter 15) moved from 10ns to 12ns.
      • Data Bus High Level Input Voltage (VIH) moved from 2.0v to 3.0v.
      • Address Bus valid after a write (parameter 22) moved from 9ns to 19ns.
      • MCBL/MP_ Low Level Input Voltage (VIL) moved from 0.8v to 0.2v.
    • 40MHz:
      • Data Bus High Level Input Voltage (VIH) moved from 2.0v to 3.0v.
      • Address Bus valid after a write (parameter 22) moved from 11ns to 21ns.
      • MCBL/MP_ Low Level Input Voltage (VIL) moved from 0.8v to 0.2v.

TMS Bug listing

  1. Back-to-Back DMA transfers between two DMA channels to/from external memory
    Problem fixed in silicon 2.0
    When one DMA channel READS a value from external memory and immediately after the other DMA channel READS or WRITES a value from or to the internal memory (or memory map registers), then, the DMA channels may transfer corrupted data. The problem may occur in the following sequences:
    • cycle 1 - DMA0 reads from external memory
    • cycle 2 - internal register cycle
    • cycle 3 - DMA1 writes to internal memory

    Value read by DMA0 is corrupted with value written by DMA1.

    or

    • cycle 1 - DMA0 reads from external memory
    • cycle 2 - internal register cycle
    • cycle 3 - DMA1 reads from internal memory

    Value read by DMA0 is corrupted with value read by DMA1.

    This problem does NOT occur if the write from one channel does NOT happen immediately after the read from the other channel. For example, the DMAs transfer data succesfully in the following sequence:

    • cycle 1 - DMA0 reads from external memory
    • cycle 2 - internal register cycle
    • cycle 3 - CPU fetches instruction
    • cycle 4 - DMA1 writes to internal memory

    To avoid this problem prevent two different DMA channels from having a back-to-back read external followed by a write internal operation or a back-to-back read external followed by a read internal. If the DMAs are synchronized to interrupts, generate a CPU interrupt that triggers the DMA by writing to the interrupt flag instead of triggering the DMA directly. This would add a few cycles between DMA operations.

  2. Back-to-Back IOSTRB read and STRB0 or STRB1 read when these are not configured for 32-bit data and 32-bit wide memory
    Problem fixed in silicon 2.0
    The 'C32 CPU or DMA may READ incorrect data from external IOSTRB memory if it is immediately followed by an external STRB0 or STRB1 memory READ when the external memory bus is NOT configured to 32 bit data and 32 bit wide memory. The problem may occur in the following sequences:
    • cycle 1 - DMA0 reads from external memory (IOSTRB space)
    • cycle 2 - CPU reads data from external memory (STRB1 space) that is configured for 16 bit data in 32 bit wide memory

    or

    • cycle 1 - CPU reads from external memory (IOSTRB space)
    • cycle 2 - CPU reads data from external memory (STRB0 space) that is configured for 32 bit data in 16 bit wide memory

    The problem does NOT occur on WRITES nor on READ-WRITE operation. The IOSTRB data may be corrupted, while the STRB0 or STRB1 data is read correctly. To avoid this problem, prevent back-to-back reads from IOSTRB and STRB0 or STRB1.

  3. Boot loading from and into the same memory strobe with different memory widths
    Problem fixed in silicon 2.0
    If the boot source resides in the same strobe (STRB0 or STRB1) as the destination of the boot source and if this write to this destiantion address requires a multicycle write (due to 8-bit or 16-bit wide memory or wait states), the data might NOT be transfered correctly.

    Due to the configurable nature of the C32 memory interface, the boot loader constantly sets the STRBx Control Register whenever it reads or writes to external memory, as in the following code:

    *====================================================================*
    * Transfer one block of data or program
    *====================================================================*
                      
                    RPTB    loop4
                    CALLU    AR1            ; read data/prg
                    STI     R4,*AR4         ; set write strobe
                    NOP                     ; pipeline
     loop4          STI     R1,*AR5++       ; write data/prg         <= Area of 
                ||  STI     R2,*AR2         ; set read strobe        <= interest
                    BU      block   ;*******; process next block
     

    The STI || STI instruction writes out the boot load value to memory and at the same time sets the STRBx Control Register memory width for the next read (32 bits wide). However, if this write is a multicycle write (due to 8-bit or 16-bit wide memory or wait states) and at the same time the STRBx Control Register (of this same STRB were the write occurs) is changed, the data might NOT be transfered correctly. This is due to a constraint in that the STRB Control Registers are statically accessed by the Memory Port during every cycle of the write operation. Hence, if the STRB Control Register is changed during or on the previous cycle of a write, the data might NOT be transferred correctly. Since the 'C32 is boot loading, the write operation can have innumerable numbers of cycles due to external hardware ready generation. To mimize this problem the setting of the STRB Control Register was moved just prior to the next read operation. This gives the greatest amount of time for the write operation.

    The new boot loader new routines are:

    *====================================================================*
    * Transfer one block of data or program
    *====================================================================*
     
            RPTB	loop4
    	CALLU	AR1		; read data/prg
    	STI	R4,*AR4		; set write strobe
    	NOP			; pipeline
    loop4	STI	R1,*AR5++	; write data/prg    <= Removed STRB setting
    	BU	block	;*******; process next block
     
      ;;;
     
    *====================================================================*
    * Read next word from boot table
    *====================================================================*
     
    read_m	TSTB	2,IOF		; handshake mode enabled ?
    	STI	R2,*AR2		; set read strobe    <==== NEW
    	BNZ	loop5		; yes, jump over
    	LDI	*AR3++,R6	; no,  just read memory & return
    	RETSU
     

    Note that this problem does not occur when boot loading from one strobe into a different strobe (i.e. STRB0 -> STRB1, STRB1 -> STRB0, IOSTRB -> STRB0, etc.)

  4. IOSTRB access followed by a IOSTRB read back-to-back with and on-chip access
    Problem fixed in silicon 2.3
    When an IOSTRB access is later followed (not necessarily back-to-back) with another IOSTRB read with an on-chip access, then the IOSTRB read will read data in the following half-cycle after IOSTRB terminated. In other words, IOSTRB performs a two and a half cycle read instead of the expected two cycle read. Due to capacitive holding, this problem might not be experienced unless the data lines were pulled high and the device was running very slow (LOPOWER mode or slow CLKIN).

TMS Additional Features

  1. 'C32 Silicon version 2.0 or greater has all the parallel instructions augmented with new operand combinations. This TechBit documents the changes to these instructions.
    Feature present in silicon 2.0 or greater.

TMS Data Sheet Corrections

  1. LOPOWER mode CLKIN to H1/H3 delay
    The maximum delay from CLKIN to H1/H3 in low power mode (LOPOWER) may be about 3-4 ns longer. This is not specified in the data sheet.
  2. LOPOWER mode CLKIN to H1/H3 delayInterrupt setup time in IDLE2
    The Interrupt setup time is 6-7 ns longer in IDLE2 mode. This is not specified in the data sheet.
  3. Corrected Reset Timing
    The reset timing in the data sheet dated prior to May 1995 is incorrect. Corrected Reset timing is provided in the TMS320C32 Data Sheet Errata or Data Sheets dated after August 1995
  4. Corrected Reset Timing Address Bus Vol parameter relaxation
    The Low Level Output Voltage (Vol) maximun for the Address Bus (A0-A23) is 0.7 v
  5. CLKIN low min pulse width (parameter 3) relaxation
    The CLKIN low minimum pulse width high [parameter 3 - tw(CIH)] for C32-50 MHz is 8 ns.
  6. CLKIN low max pulse width (parameter 3) relaxation
    The CLKIN low maximum pulse width high [parameter 3 - tw(CIH)] for C32-40 and C32-50 operating at 3.3 MHz is 10 ns.
  7. Note added in parameter 95, hold time for general purpose output to input after H1 high
    Add note to Parameter 95 [th(H1H)] - Hold time for peripheral pin changing from general-purpose output to input mode after H1 is high that states it is assured by design but not tested.
  8. Deletion of enable time /SHZ high to all pins active, parameter 105
    Parameter 105 [ten(SHZ)] - Enable time for all output and I/O pins once /SHZ signal goes high has been deleted.

Updated on:
June 15, 1997

 

Under certain conditions the DSP is seen to fetch corrupt data.  This condition is only seen to occur in the two instruction loop when the DSP is clearing the data in a TDC chip after the maximum number of hits have already been read.  The conditions are that the DSP is reading a register using IOSTROBE in a two instruction loop.  The branch instruction is fetched before the register is read, as expected from the pipeline operation.  Sometimes, but not always, the lower data lines oscillate.  These oscillations seem to be driven by the DSP.

The instructions in the loop which cause the failure are shown in this code fragment.  They are the two instructions, LDI and BNN, following SL0A_READALL:x:

SL0A_HAD_TRAIL:x:
	BRD SL0A_BUILDHIT:x:	; delayed branch - go to the hit-building block
	LDI R1, R5	        ; start time of pulse is time of unpaired edge
	LDI 0, R4		; pulse width for unpaired trailing edge is 0
	CMPI 1h, R7		; How many hit words has the DSP stored for
				; this TDC channel?
	
SL0A_READALL:x:			; this code reads a channel until empty
	LDI *+AR3(IR0), R1	; load the contents of the IR0th TDC into R1
	BNN SL0A_READALL:x:	; read channel again if not negative
	
SL0A_END:x:
	ADDI 1, IR0		; increment TDC counter

These two instructions are replaced with a delayed branch, which seem to work ok:

SL0A_HAD_TRAIL:x:
	BRD SL0A_BUILDHIT:x:	; delayed branch - go to the hit-building block
	LDI R1, R5	        ; start time of pulse is time of unpaired edge
	LDI 0, R4		; pulse width for unpaired trailing edge is 0
	CMPI 1h, R7		; How many hit words has the DSP stored for
				; this TDC channel?
	
SL0A_READALL:x:			; this code reads a channel until empty
	LDI *+AR3(IR0), R1	; load the contents of the IR0th TDC into R1

*** The order of the following 4 instructions is crucial!  Never change it.
SL0A_READLOOP:x:	
	BNND SL0A_READLOOP:x:	; read channel again if not negative
	NOP
	LDI *+AR3(IR0), R1	; load the contents of the IR0th TDC into R1
	NOP
		
SL0A_END:x:
	ADDI 1, IR0		; increment TDC counter

After seeing the problem with this program we wrote another version which just looped in this part of the code.  We replaced large sections of the other code with jumps back to the start.  This allowed the error to occur, sending the DSP to any address, and the program would just start over again.  We triggered the logic analyzer on one of the addresses showing up which could only be gotten to by jumping to the wrong address.

This picture shows the signals around the time of the loop being executed when no problem occurs.  The LDI instruction is at 002D2B and the BNN instruction is at 002D2C.  The register being read is 81050B.

This shows what happens when the data lines oscillate.  The data during the fetch of the BNN instruction, right before the G2 marker, is oscillating.  Instead of branching back to 002D2B it branches to 002D27.

 

This picture is an expansion around the time the oscillations occur.

This picture is an expansion at the resolution of the logic analyzer:

The scope trace below shows the data lines at the time of the error.  When STROB0 goes high near the middle of the picture is when the data is latched by the DSP on the falling edge of H1.

The orange trace is the data line, the green is H1, and the violet is STROB0.  The leads on the scope probe are about 1 inch long, and the ground connection for the scope probe is 0.1" from the signal.