Schematics
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The schematics for the Cluster List Board are on 11x17 paper.  On most printers this is the Ledger paper size.

Sheet 1   Connectors to Channel Link Error Checker
Sheet 2   HOTLink Receivers and LVDS Receiver from CLIQUE
Sheet 3
Sheet 4   Seed Selection and Crate Addresser   and FIFO Control
Sheet 5   Adding of EM and HAD Energies
Sheet 6   Adding the Total Number of Towers in the Cluster
Sheet 7   Xilinx that Controls Internal Signals Related to MB
Sheet 8   FIFOs that Store the Data Before the MB
Sheet 9  FIFOs that Store the Data Before the MB
Sheet 10   Magic Bus Buffers
Sheet 11   P0 Backplane Connector
Sheet 12   P1 Backplane Connector
Sheet 13   P2 Backplane Connector
Sheet 14   P3 Backplane Connector
Sheet 15   Misc. Controls and Signals
Sheet 16   Decoupling Capacitors and Power Spike Fuses
Sheet 17   Breakout of Signals to Diagnostic Connectors
Sheet 18   Breakout of Signals to Diagnostic Connectors

Xilinx Chip Schematics

Sheet 1   Outputs a 32 Bit Address to the Magic Bus
Sheet 2   Outputs a 32 Bit Address to the Magic Bus
Sheet 3   Controls for FIFO Write Cycle
Sheet 4   Controls for MB/FIFO Read Cycle
Sheet 5   Controls for MB/FIFO Read Cycle
Sheet 6   Create Strobe for the MB ADs Needed When BOSS
Sheet 7   EV Loaded Signals