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Requirements Discussion TOC

Requirements Discussion

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Table of Contents

TDC Myron 25 Oct 1997
Re: TDC - Minutes from data format meeting Myron 06 Nov 1997

TDC data format: what's available Mike Kelly 06 Nov 1997
Re: TDC data format: what's available Mike Kelly 11 Nov 1997
Re: TDC data format: what's available (Response) Jim Patrick 13 Nov 1997

Re: TDC data format: what's available (Response) MALAYSIA 24 Jul 1998

Re: TDC data format: what's available Jonathan Lewis 17 Nov 1997

Re: TDC data format: what's available 13 Dec 1997

Re: TDC data format: what's available Tom LeCompte 16 Dec 1997

Run 2 TDC96 online diagnostics Mike Kelly 07 Nov 1997

TDC local (DSP) code development: Overview Mike Kelly 07 Nov 1997

TDC96B Tests And Results Mike Kelly 04 Dec 1997
TDC96B tests of the Address Space Mike Kelly 04 Dec 1997

Tests of Xilinx FPGA and DSPs Mike Kelly 04 Dec 1997

Tests of the TDC chips and PALS Mike Kelly 04 Dec 1997

Tests of TDC chips and PALs (part II) Mike Kelly 10 Dec 1997

Re: TDC96B Tests And Results L2 Accept processing time for TDC96B 13 Dec 1997

The Xilinx Beam Crossing Counter Mike Kelly 13 Dec 1997
Re: The Xilinx Beam Crossing Counter (Fixed!) Mike Kelly 15 Dec 1997

Tests of the Mezzanine Card Interface Mike Kelly 19 Dec 1997
Re: Tests of the Mezzanine Card Interface Mike Kelly 08 Jan 1998

Re: Tests of the Mezzanine Card Interface Mike Kelly 14 Jan 1998

Modifications made to existing TDC96Bs Mike Kelly 04 Dec 1997
TDC96B Components not installed by ADCO (3 Dec 97 boards) Mike Kelly 04 Dec 1997

Fix for ID RAM LACK# Mike Kelly 04 Dec 1997
Re: Fix for ID RAM LACK# (correction) Mike Kelly 23 Jan 1998

Fix for TDC_RESET (R7 pins 14 and 15) DM96LS02 Mike Kelly 04 Dec 1997

TDC PALs have wrong pad assignments Mike Kelly 04 Dec 1997

Fanout Q8 has an open Output Enable Mike Kelly 04 Dec 1997

Changes made to the Mezzanine Timeout circuitry Mike Kelly 09 Jan 1998

Modification made to FPGA PROG*, Control Register Mike Kelly 14 Jan 1998

MEZZ_RESET*  change made on CMP mezzanine card Mike Kelly 14 Jan 1998

Fix for FIFO (Empty/Full Reporting) Mike Kelly 12 Feb 1998

Modifications to properly time L1BA and L1Accepts Mike Kelly 08 Mar 1998

Pull-down resistor (1k) installed on TDC96B L2A Mike Kelly 16 Mar 1998

Future Modifications to TDC96 Mike Kelly 04 Dec 1997
Suggested fix to enable the ID RAM Mike Kelly 04 Dec 1997

Suggested Fix for R17 and R7 Mike Kelly 04 Dec 1997

Suggestion to move DSP diagnostic connector Mike Kelly 04 Dec 1997

Suggestion to fix component Q8 Mike Kelly 04 Dec 1997

Suggestion regarding Circuit Break and DC-DC converter Mike Kelly 04 Dec 1997

Fixes for incorrect geometries/pad sizes Mike Kelly 04 Dec 1997

Call for suggestions for DSP interrupts Mike Kelly 04 Dec 1997

Suggestion for silkscreen changes Mike Kelly 11 Dec 1997

GA*(4 0) needs to be in a register Mike Kelly 18 Dec 1997

Relative Cost of the TDC96 FIFO components Mike Kelly 18 Dec 1997

Suggestion for Xilinx reset procedure Mike Kelly 18 Dec 1997
Re: Suggestion for Xilinx reset procedure Mike Kelly 08 Jan 1998

Re: Suggestion for Xilinx reset procedure (with MEZZANINE CARDS) Mike Kelly 08 Jan 1998

Re: Suggestion for Xilinx reset procedure Mike Kelly 14 Jan 1998

Changes to the Mezzanine PAL and Diagnostic Connector Mike Kelly 09 Jan 1998

Minor change to schematics page 25 Mike Kelly 09 Jan 1998

FIFO_R* generation needs to be corrected Mike Kelly 12 Feb 1998

Johns Hopkins' TDC96B Mike Kelly 14 Jan 1998
Status of TDC96B as it left Michigan Mike Kelly 14 Jan 1998

TDC DSP timing measurements Mike Kelly 14 Nov 1997
TDC96B timing measurements Mike Kelly 13 Dec 1997

Re: TDC DSP timing measurements Mike Kelly 18 Dec 1997

Request for modification of cdf_clk signal on TDC Eric James 10 Dec 1997

Alpha Processor Board Zhihui 29 May 1998
Re: Alpha Processor Board Zhihui 29 May 1998

MAGICPCI reminder Zhihui 09 Jun 1998
Re: MAGICPCI reminder Stephen 10 Jun 1998

S82378ZB obsolete zhihui 18 Jun 1998

MagicIo FPGA Zhihui  05 Jun 1998
Usage of this discussion Zhihui 05 Jun 1998

Design Directory & specification zhihui 05 Jun 1998

The power of LogiBLOX zhihui 05 Jun 1998

Xilinx hot line support zhihui 05 Jun 1998

Xilinx distributor for quote zhihui 17 Jun 1998

Xilinx BUFE and BUFT zhihui 05 Jun 1998

MAGICIO FPGA bug log 1 Zhihui 09 Jun 1998
MAGICIO FPGA bug log 2 Zhihui 09 Jun 1998

dsgnmgr report for the first MAGICIO compile Zhihui  10 Jun 1998

Design and Test Document zhihui 17 Jun 1998
Pin out constraint zhihui 17 Jun 1998
Re: Pin out constraint Zhihui 26 Jun 1998

Antigravity joshua.gulick@cheerful.com 4/25/99
Xilinx Chip S.O.S. LEE G. DENEAULT 3/7/00

This work is supported by the University of Michigan and by the Department of Energy.
For problems or questions regarding this web contact myron@umich.edu.
Last updated: February 15, 2002.