Version 0.1

21 October 1997

TDC Data Processing and Format

Mike Kelly

Abstract

The Run 2 TDC96 boards contain a local microprocessor (a DSP) which constructs hit words from the edge data stored in one of the four Level 2 buffers inside each of the 96 TDC chips. The local microprocessor makes the hit words available to other in-crate devices by storing the data in a FIFO accessible by VME reads. This document describes how the DSP processes TDC edge data and defines the format of the hit words. Some preliminary results of processing times are also included.

Local DSP Processing: TDC readout

Each TDC96 has a local digital signal processor with 32K of available Static RAM. The DSP used is a Texas Instruments TMS320C32. The DSP monitors the Level 2 Accept (L2A) signal on the CDF VME backplane. Upon witnessing a L2A the DSP must poll TDC chips for valid wire data. There `C32 allows some flexibility in the readout of the TDC chips. Two methods are described below:

1. CPU only: The DSP can be programmed to have dedicated machine instructions for the purpose of reading the TDC chips in a loop. Every channel is read until it is empty. This method is straightforward, but since the CPU can only be used for one task at a time.

1. CPU with DMA support: The `C32 is equipped with a Direct Memory Access controller which can operate independently of the CPU. It is possible for the DMA to perform TDC reads while the CPU is used to perform some other function such as constructing header word fragments. This method requires detailed management of DSP resources, such as internal DSP SRAM to avoid CPU-DMA conflicts.

Local DSP Processing: Building Hit Words

Each TDC chip records tracking chamber wire transitions, either low to high (as 0 1) or high to low (as 1 0). These leading or trailing edges are stored along with the time they passed out of the TDC digitizing buffer relative to a L1 Accept, up to a maximum time of 2047 nanoseconds. The DSP has the duty to construct hit words from a given channels edges. A 32-bit hit word has the following format:

The width of a pulse is determined from the time of a trailing edge relative to the immediate leading edge. If the TDC recorded an unpaired leading edge the DSP fills bits (21 11) with 1s, if the TDC recorded an unpaired trailing edge, the DSP sets the pulse width to 0.

While the DSP is reading TDCs, building hit words and transferring data to the VME FIFO, it drive the VME backplane signal LOCAL_DONE low through an open collector. When a TDC96 finishes processing a L2A, it releases LOCAL_DONE.

Once the DSP has emptied all the TDCs and finished building hit words, it constructions a 32-bit header word which will precede all the hit words in the VME FIFO. The purpose of the header word is to inform the device which is reading the TDC96 how many hit words are stored in the TDC96 VME FIFO. The format of the header word is not yet defined, but for the purposes of prototype TDC tests, the following format was used:

Note that the EVID bits are in reverse order, this is because of a TDC16B peculiarity. The TDC96 VME FIFO can store a maximum of 1024 words, including the header word, so only bits (9 0) need to be dedicated to the count of the hit words. This makes thirteen more bits (22 10) available for some other use. It is forseen that eight bits will be used for an 8-bit bunch counter.

Local DSP Processing: Preliminary Results

The prototype TDC16B, a 16-channel version of the TDC96, was used to time the local processor from the arrival of L2A to the deassertion of LOCAL_DONE. The CPU-only method of TDC polling is the only version tested so far. About 20 microseconds were needed for the DSP to perform the basic duty of constructing the header word. It took the DSP ~45 secs to poll all 16 channels and learn that they were empty, and construct the header word. If all 16 channels have 1 pulse (each pulse having two edges) it took the DSP ~124 secs to read all the edges, construct hit words and then construct the header word.