Version 1.4

19 February 1998

TDC96B Address Space

Mike Kelly

 

Memory

Static RAM: Local: 0x0 - 0x007fff VME: 0x0 - 0x0001fffc (32k)

Local: 0x0 - 0x03ffff VME: 0x0 - 0x000ffffc (256k)

The TDC96B is configured with a block of either 32k or 256k SRAM. The words in SRAM are 32 bits wide. The DSP will load and execute its program from SRAM.

ID RAM: Local: 0x040000+ VME: 0x00100000+

The TDC96B has a single 8-bit wide block of static RAM which serves as the ID PROM, as specified in CDF NOTE 2388. Since static RAM are not retained when power is turned off, the contents of the ID PROM are constructed by the local TDC96B processor (DSP) as part of the TDC96B initialization. The contents of the ID PROM are stored in non-volatile FRAM0. Following the format specified in CDF NOTE 2388:

Local

VME

(31 24)

(27 0)

0x04 0000

0x00100 000

Serial Number [3]

-

0x04 0001

0x00100 004

Serial Number [2]

-

0x04 0002

0x00100 008

Serial Number [1]

-

0x04 0003

0x00100 00c

Serial Number [0]

-

0x04 0004

0x00100 010

0x20 (ASCII blank)

-

0x04 0005

0x00100 014

Board Type [2]

-

0x04 0006

0x00100 018

Board Type [1]

-

0x04 0007

0x00100 01c

Board Type [0]

-

0x04 0008

0x00100 020

User Specified

-

0x04 0009

0x00100 024

User Specified

-

0x04 000a

0x00100 028

User Specified

-

0x04 000b

0x00100 02c

User Specified

-

0x04 000c

0x00100 030

User Specified

-

0x04 000d

0x00100 034

User Specified

-

0x04 000e

0x00100 038

User Specified

-

0x04 000f

0x00100 03c

User Specified

-

 

 

Flash RAM 0: Local: 0x900000 - 0x91ffff VME: 0x02400000 - 0x0247fffc

The TDC96B has a single 128k block of 8-bit wide FRAM. The DSP’s program is stored

in FRAM0. Upon a DSP reset, the 8-bit program fragments are loaded from FRAM0, built into 32-bit wide machine instructions, and then stored in SRAM.

 

Flash RAM 1: Local: 0x920000 - 0x93ffff VME: 0x02480000 - 0x024ffffc

The TDC96B has a second 128k block of Flash RAM (FRAM1) which contains the

Xilinx programs for the TDC and Mezzanine board. FRAM1 is by default only 8-bits wide, but can be expanded in bytes-sized increments up to a width of 32-bits, should extra memory be needed.

Registers

Control Register: Local: 0x810000 VME: 0x02040000

31

30

29

28

SELECT (SEL)

REG_EV_CTL

TDC_SFT_RESET

DSP_SFT_RESET

R/W

R/W

R/W

R/W

27

26

25

24

DSP_BOOT_DONE

LOCAL_DONE

XI_PROG/XI_DONE

MEZZ_TO_RESET

R/W*

R/W

R/W

R/W

23 22 21 20

19 18 17 16

15 14 13 12

11 10 9 8 7 6 5 4 3 2 1 0

unused

unused

unused

unused

x x x x

x x x x

x x x x

x x x x x x x x x x x x

The Control Register serves as a register that sets and reports a variety of control signals relevant to the operation of the TDC96B.

 

Bit

Name

Status

Function

31

Select (SEL)

R/W

This bit chooses the data inputs of the TDC chips. 1: Data is input from the front panel

0: Data is input from the calibration cell

30

REG_EV_CTL

R/W

This bit chooses the input to the Event Register

1: ER is controlled by writes to that register

0: ER reports the state of the backplane signals

29

TDC_SFT_RESET

R/W

TDC Software Reset: Setting this bit to 1 causes the TDC chips to be put into reset. It is not self-clearing; it must be set to 0 to complete the TDC reset.

28

DSP_SFT_RESET

R/W

DSP Software Reset: Setting this bit to 1 causes the DSP to be put into reset. It is not self-clearing; the DSP is held in reset until this bit is set to 0.

27

DSP_BOOT_DONE

R/W

This bit will be set to 1 by the DSP when it begins executing its program from SRAM. It is used as a signal to the Interrupt PAL. After this bit is asserted, the DSP will accept interrupts.

26

LOCAL_DONE

R/W

The DSP will write a 1 to this bit while it is reading TDCs and constructing hit-words. This will use an open collector to drive the backplane signal CDF_TDC_DONE LO. The TDC96Bs will not be sent another L2 accept until this signal is not driven, so the DSP will write a 0 to this bit upon completion of its readout duties.

25

XI PROG/DONE

R/W

This bit reads as 1 when the Xilinx chips have been successfully programmed. Writing a 0 to this bit holds the Calibration Cell’s DONE_PROG# pin low.

24

MEZZ_TO_RESET

R/W

When read, this reports if no Mezzanine Card responded within 800 nanoseconds of an attempted access. (1 means that the transaction timed-out.) Writing a 1 to this bit clears the timeout condition. The bit is not self-clearing.

 

 

Status Register: Local 0x810100 VME: 0x02040400

31

30

29

28

Empty FIFO (EF)

Full FIFO (FF)

Half-full FIFO (HF)

Empty FIFO 1 (EF1)

R

R

R

R

27

26

25

24

Empty FIFO 2 (EF2)

Empty FIFO 3 (EF3)

Interrupt 0 (INT0)

Interrupt 1 (INT1)

R

R

R

R

23

22

21

20

Interrupt 2 (INT2)

Interrupt 3 (INT3)

CDF_TDC_DONE

LOCAL_DONE

R

R

R

R

19

18

17

16

Xilinx Initialize (INIT)

unused

unused

unused

R

x

x

x

15 14 13 12

11 10 9 8

7 6 5 4

3 2 10

unused

unused

unused

unused

x x x x

x x x x

x x x x

x x x x

 

The Status Register is a read-only register which reports the status of various TDC96B components.

 

Bit

Name

Function

31

Empty FIFO (EF)

This bit reads 1 when there is no data in the FIFO

30

Full FIFO (FF)

This bit reads 1 when the output FIFO is full.

29

Half-full FIFO

This bit reads 1 when the FIFO contains 513 or more words.

28

EF1

This bit reads 1 when there is no data in the FIFO

27

EF2

This bit reads 1 when there is no data in the FIFO

26

EF3

This bit reads 1 when there is no data in the FIFO

25

INT0

This bit reads 1 while the DSP is receiving an interrupt from INT0.

24

INT1

This bit reads 1 while the DSP is receiving an interrupt from INT1.

23

INT2

This bit reads 1 while the DSP is receiving an interrupt from INT2. In order for the DSP to correctly find its program in FRAM0, INT2 must be asserted during the DSP’s reset procedure.

22

INT3

This bit reads 1 while the DSP is receiving an interrupt from INT3.

21

CDF_TDC_DONE

This bit reports the state of the backplane. If any TDC96B in the same crate is not finished building hit-words, this bit will read as a ‘1’

20

LOCAL_DONE

This bit will read 1 while this TDC96B is driving CDF_TDC_DONE LO.

19

INIT

This bit reads 0 while the Xilinx chips are clearing their configuration memory. The DSP must monitor this bit so that serial Xilinx programming starts after this bit is 1.

 

 

 

Event Register: Local 0x810200 VME: 0x02040800

 

31

30

29

28

Level 1 Accept (L1A)

L1 Buff Addr1 (L1BA1)

L1 Buff Addr0 (L1BA0)

Level 2 Accept (L2A)

R/W*

R/W*

R/W*

R/W*

27

26

25

24

L2 Buff Addr1 (L2BA1)

L2 Buff Addr0 (L2BA0)

Scan List 2 (SL2)

Scan List 1 (SL1)

R/W*

R/W*

R/W*

R/W*

23

22

21

20

Scan List 0 (SL0)

ABORT

HALT

STOP

R/W*

R/W*

R/W*

R/W*

19

18

17

16

RECOVER

TEST

RUN

Bunch 0 (B0)

R/W*

R/W*

R/W*

R/W*

 

15

14 13 12

11 10 9 8

3 2 1 0

Beam Crossing (BC)

unused

unused

Event ID (EVID 3 0)

R/W*

x x x

x x x x

R/W*

 

 

The Event Register reports the status of signals from the Trigger System Interface (TSI) and the Master Clock to the TDC96B. The Event Register is read-only, unless bit 30 of the Control Register (REG_EV_CTL) is set to 1, then the contents of the Event Register can only be changed by directly writing to that register. When in read-only mode, the unshaded bits of the Event Register are updated on each rising edge of CDF_CLOCK. The shaded bits are only updated in the register upon receipt of a Level 2 Accept.

 

 

Bit

Name

Function

31

L1A

Level 1 (L1) Accept

30

L1BA1

Level 1 accept Buffer Address bit 1

29

L1BA0

Level 1 accept Buffer Address bit 0

28

L2A

Level 2 (L2) Accept

27

L2BA1

Level 2 accept Buffer Address bit 1

26

L2BA0

Level 2 accept Buffer Address bit 0

25

SL2

Scan List identifier bit 2

24

SL1

Scan List identifier bit 1

23

SL0

Scan List identifier bit 0

22

ABORT

Abort Gap marker

21

HALT

When this bit reads 1, the TDC96B is to stop filling the L1 FIFO/pipelines. The HALT condition is set by CDF_STOP and cleared by CDF_RUN.

20

STOP

This bit reads 1 when CDF_STOP is asserted

19

RECOVER

When this bit reads 1, the DSP should reset the FIFO/pipelines.

18

TEST

This bit reads 1 when CDF_TEST is asserted.

17

RUN

This bit reads 1 when CDF_RUN is asserted.

16

B0

This bit reads 1 during Bunch 0

15

BC

This bit reads 1 during Beam Crossings

14

EVID0

Bit 0 of the DAQ Event ID

13

EVID1

Bit 1 of the DAQ Event ID

12

EVID2

Bit 2 of the DAQ Event ID

11

EVID3

Bit 3 of the DAQ Event ID

 

 

FIFO Write Register: Local: 0x810300 VME: 0x02040c00

FIFO Read Register: Local 0x810400 VME*: 0x00080000

Header Word Format

(31 23)

(22 20)

(19 18)

(17 8)

(7 0)

Module ID

(User-specified)

Scan List (2 0)

L2BA (1 0)

Data Word Count

Corrected Beam Crossing Count

R

R

R

R

R

Data Word Format

31

(30 22)

(21 11)

(10 0)

First hit on channel

TDC channel #

Pulse width

Hit time

1 = yes, 0 = no

Defined by look-up table

R

R

The TDC96B has FIFO capable of storing 1024 32-bit words. The DSP will convert the edge information recorded by the TDC chips into hit words. These hit words will have the format described above. Each group of hit words from a Level 2 Accept will be preceded by a special word describing the number of hit words which follows it. The FIFO is four Cypress CY7C425s, which are pin-compatible with larger Cypress FIFOs capable of storing 2048 (CY7C429) and 4096 (CY7C433) words.

*It is important to note that the FIFO can be read from VME only by means of dedicated circuitry; this corresponds to a unique VME address. Shifting the DSP’s FIFO Read Register address by 2 bits will not result in a FIFO read.

The DSP processes a L2 accept by reading the TDC channels not marked "dead" in the skip list. When it is done reading TDCs, it puts a header word into the VME FIFO. The header word contains a word count of how many data words have been put behind the header word into the FIFO.

The pulse width of an unpaired leading edge is set to all ones. The pulse width of an unpaired trailing edge is set to all zeros.

TDC Registers: Local 0x810500 - 0x81055F VME: 0x02041400 - 0x0204157c

31

(30 12)

11

(10 0)

TDC Empty

unused

Edge Sense

Edge Time

There are 96 read-only TDC registers on the TDC96B, one for each of the 96 TDC channels. The address decoding circuitry interfaces with the TDC chips by means of a TDC PAL. Each TDC PAL handles a group of four TDC chips. A read of a TDC Register will result in a 32-bit word with the following format:

Bit

Name

Function

31

TDC Empty

This bit will read 0 if the edge word is valid.

This bit will read 1 if the TDC contains no more edge words.

30 - 12

unused

These will be read as 1

11

Edge Sense

This bit will read 1 if the edge is from low to high

This bit will read 0 if the edge is from high to low

10 - 0

Edge Time

These bits specify when the edge occurred relative to the beam crossing, in nanoseconds.

 

 

 

Calibration Registers: Local 0x810600 - 0x81065F

VME: 0x02041800 - 0x0204197c

(31 4)

3 2

1

0

unused

unused

Calib Select Addr bit 1

Calib Select Addr bit 0

-

-

R/W

R/W

There are 96 registers which allow backplane calibration signals to be sent to the TDC chips. There is a one-to-one correspondence between Calibration registers and TDC chips. The first calibration register is for TDC 0 and the last is for TDC 95. A write specifies which calibration signal is sent to the multiplexer controlled by the Select bit (31) of the Control Register. A read of a Calibration Register will report which calibration signal is being sent to the TDC chip’s multiplexer:

Calibration Select Address (00): No calibration signal is used.

Calibration Select Address (01) CDF_TDC_CALIB0* is used.

Calibration Select Address (10) CDF_TDC_CALIB1* is used.

Calibration Select Address (11) CDF_TDC_CALIB2* is used.

 

Bit

Name

Function

31 - 2

Unused

Read as 1, writes have no effect.

1 - 0

Calibration Select

Address Bits

During writes, these bits specify which calibration signal is sent to the TDC chip. During reads, these bits specify which calibration signal, if any, is being

sent to the corresponding TDC chip.

 

 

 

Beam Crossing Counters (BCC): Local: 0x810660 - 0x810663

VME: 0x02041980 - 0x0204198c

(31 16)

15 14 13 12

11 10 9 8

(7 0)

unused

unused

unused

Beam Crossing Count

-

-

-

R/W

There are four BCC on the TDC96B which count the number of CDF clock cycles after a Level 1 Accept. The four BCC each correspond to a single Level 1 TDC buffer, specified by the Level 1 Buffer Address (L1BA). During the processing of a Level 2 Accept, the DSP reads the appropriate BCC and subtracts the L1 decision time (42 beam crossings) to determine the corresponding beam crossing for a given L1A. The BCC count from 0 to 158 and are reset upon bunch zero (B0).

Bit

Name

Function

31 - 8

Unused

Read as 1, writes have no effect.

7 - 0

Beam Crossing Count

Return the number of CDF clock cycles since the last Level 1 Accept for a given L1BA. Writes have no effect.

 

Mezzanine Card Registers: Local: 0x810700 - 0x8107ff

VME: 0x02041c00 - 0x02041ffc

(31 24)

(23 16)

(16 8)

(7 0)

MEZZ_DATA (7 0)

unused

unused

unused

R/W

-

-

-

The data to be written to/read from the 8-bit mezzanine card bus occupies the most significant byte of the local TDC96 DATA (31 0) bus.