Developing Mezzanine Cards
M. Campbell, J. Chapman, E. James, M. Kelly, C. Murphy, D. Winn, D. Wolinski
Requirements and Card Count
Almost all of the TDC cards will require some form of mezzanine card to either generate the Level 1 trigger primitives or to prepare and transmit the raw hits to some other card that will prepare the primitives. This document is intended to provide the information needed by the designers of these mezzanine cards. There are specifications relating to the physical size and clearance of the card, specifications regarding the power and voltage levels available to the card, connector specifications and pin assignments, and specifications regarding the serial and parallel bus programming features available on the card. The table below gives the current channel count for the TDCs and an approximate number of TDC and mezzanine cards needed. The number of TDCs differs from the number of mezzanine cards since only those channels used in the trigger need have mezzanine cards. There are a minimum of three (3) different mezzanine card designs and possibly more. The COT will certainly have a design unique to it. The muon time difference measurements needed for the CMU, CMX, and IMU will likely all be handled by a single Dt selecting card. The programmable Xilinx based trigger card designed for the CMP pattern finding could potentially be programmed to do all the scintillator and Hadron TDC bit gating and multiplexing. The mezzanine card counts assume that the axial COT wires and the outer most stereo layer are instrumented with finder circuits and that only the mean-timed CSX scintillator signals are instrumented.
Connections and Signals
A diagram of the mezzanine card is shown below in Fig. 1. The connector labeled #1 is located interior on the board and delivers signals which are replications of the inputs to the TDC. These signals are labeled wire_data_nn in Table 2, where nn is the channel number in the TDC. The remaining connectors labeled #2 and #3 are anterior on the card and connect primarily to P3 on the VME backplane. Tables 3 and 4 provide the pin assignments for these anterior connectors. The signals represented on these connectors are defined by the designer of the mezzanine card to fulfill the function required of the board. Connectors #2 and #3 contain several control lines to the mezzanine card from the TDC for programming the Xilinx or programming constants into the Xilinx or other custom chips on the mezzanine card.
The 140 pin connectors (#1, #2, and #3), defined in Tables #2, #3, and #4, are of AMP manufacture and are units in the CHAMP 0.8mm FH series. The connector mounted on the TDC board is AMP 5-179009-6 (the receptacle) and its mating partner on the Mezzanine card is 179031-6 (the plug). The TDC mounted receptacle, 5-179009-6, is sold in only one height. The mezzanine card plug, 179031-6, is one of a series that are manufactured in several heights. These mating connectors are illustrated in Fig. 2 below. In the figure the board separation (called stack height) is listed with the range 5.00-16.00mm. The 179031-6 is one specific height selected such that the board separation is 12mm.
The CDF control signals to the mezzanine card are not the CDF control signals as they appear on the backplane. These signals have been processed within the TDC. They are different in two distinct ways, they are logically inverted relative to the backplane signals and most have been latched on the rising edge of CDF_CLK and thus change each 132ns. The labels in Table 2 indicate the inversion only. The signals that have no storage latch are a) CDF_L1A which rises with CDF_CLK and falls with the deassertion of backplane signal CDF_L1A* and b) CDF_L1_BUFF0 and CDF_L1_BUFF1 which are simple inversions.
The transmitted signals from the mezzanine card route to the hard metric connectors, J3(J5/J6), of the VME backplane. The signals and pin assignments for the mezzanine connectors #2 and #3 are represented in Tables 3 and 4 below. In these tables signal names are chosen as the connector, row, and column of the hard metric connector so as to not introduce additional names that have no meaning except as intermediaries. In the corresponding tables for the connectors J3(J5/J6), Tables 5 and 6, the names define the connector and pin location on the mezzanine card connectors #2 and #3.
The 140 pin mezzanine card plug is shown in Fig. 3.
Downloading Mezzanine Card Setup Data
In general the mezzanine cards are expected to need setup programming. The cards designed to date use Xilinx chips and custom trigger chips that require the downloading of Xilinx programming and setup constants. The protocol adopted for the Xilinx programming is dictated by the Xilinx design. For the custom trigger chips a serial protocol has been defined similar to that used by the Xilinx programming but without the serial chaining permitted by the Xilinx chips. For setup constants contained within the Xilinx (but not part of the circuit programming), a parallel bus protocol is defined. In general there are three different programming sequences required to initialize the most general mezzanine card.
- Xilinx serial logic programming of any Xilinx chips on the board as required to defined its inputs, outputs, and electronic functions.
- 8-bit parallel programming of any Xilinx chip constants as needed by the circuits to set thresholds or trigger parameters. Each Xilinx chip is expected to connect to the 8-bit bus in parallel as a slave unit, making use of a unique address range among those available to determine when it is being addressed.
- 8-bit parallel programming of data to a specific Xilinx chip responsible for loading the custom trigger chips contained on the mezzanine card. The protocol used to load the custom trigger chips is not specified in this document and is unique to the trigger chips being used. For the muon Dt chip the serial protocol is defined in terms of a simple chip enable, serial clock, and serial data for each custom chip. The serial data and serial clock can be distributed to all chips with the enable determining which chip receives the data. If the same data is destined for all custom chips, then all enables can be set and one copy of the serial data loaded to all units.
Xilinx Logic Program Loading
The Xilinx serial programming protocol employs 6 signals as defined in Table 7 below.
Fig. 4 The serial programming sequence. Each device intending to receive setup bits from the TDC must await the PROG* line going "False" at which time it should drive the INIT* line "False", perform any necessary initializations, and then release its drive of INIT*. The time the last device releases the drive of INIT* will be sensed by the DSP and output SDATA will then be presented with SCLK clock transitions. When the last device has accepted its data all devices will release the DONE line allowing it to return "True". The RESET* line should be ORed with the PROG* line for Xilinx 3000 series. For Xilinx 4000 series the RESET* line is user defined and should not be ORed with the PROG* line.
Fig 5. The proposed TDC to Mezzanine card control logic. In order to accommodate both Xilinx 3000 series and 4000 series units with the same DSP output connections, the above pattern of logic is recommended. The circuits on the left are on the TDC card and those items on the right represent connections on the mezzanine card.
Xilinx Parameter Loading
Fig. 8 shows a Xilinx 3000A series (Mentor Graphics interface) implementation of the TDC-Mezzanine protocol. In this example, the upper 4 address bits identify a particular Xilinx chip, and the lower 4 address bits identify an internal 8-bit register on that chip. This scheme allows for a maximum of 16 different Xilinx chips on the mezzanine card, each with 16 internal 8-bit registers (128 bits). The 4-bit comparator (comp4) may be eliminated in favor of an external 4-bit decoder and an additional input pin (providing signal CS). The main advantage of doing this is that each Xilinx chip can then remain ignorant of its own 4-bit chip address, eliminating the need to generate a different Xilinx program for chips that are otherwise identical in function. This example allows storage of 64 user-defined bits in DATA[63:0]. Note that since only 8 internal registers (fd8ce) are used, the address acknowledge (AK*) is only generated if an existing internal register was selected. In general, if n internal registers are used for user data, then an n-input OR should be used to generate the internal signal AK. Since the protocol signals AK*, DK* are daisy-chained among every Xilinx chip on the mezzanine, they are generated by tri-state output buffers (obufe) on each chip. When the signal is not driven low by any Xilinx, it should be pulled up to VCC by an external resistor (~2Kohm is appropriate) on the mezzanine. During a TDC read cycle (see Fig. 8), the mezzanine drives the requested data onto AD[7:0]. Because of the capacitive load present on the AD bus (the value is presently unknown), the driving Xilinx must delay the (low) assertion of DK* for some time. This delay (50 ns here) is generated by the six buffers (buf) preceding the multiplexer (m2_1) in this example. In general, the delay between DS* (H->L) to DK* (H->L) during a TDC read is given by 20ns + 5ns x (# of buffers). Mentor Graphics users should note that the pin of each buffer (buf) must be given a special property (property name = X, property value = X, meaning "explicit"). This ensures that the buffer is included in a separate CLB (from the CLB generating the input to the buf) and is not optimized away when the design is compiled. The approximate resource usage of the Xilinx 3000A series chip for access to n internal 8-bit registers (including internal 4-bit comparator) is listed at the top of the schematic of Fig. 8.
Mezzanine register access by the TDC is accomplished through an asynchronous protocol. In addition to a multiplexed 8-bit address/data bus, there are five control signals that implement the protocol as defined in Table 8 and exhibited in the timing diagrams for read and write cycles shown in Figs. 6 and 7. Times given with a "greater than" (>) sign indicate guaranteed minimum setup and hold times. Note that the timing for the mezzanine signals, AK* and DK*, were measured from a Xilinx 3020A implementation. In both diagrams, each cycle consists of two parts: an address cycle and a data cycle. During the address cycle, the TDC drives the address onto the AD bus for a minimum of 50ns setup time until giving the address strobe AS*. The TDC then waits for the mezzanine to acknowledge the address. The behavior during the data cycle depends upon whether the cycle if a read or write.
If the cycle is a write, the TDC then drives data onto the AD bus for a minimum of 50ns until giving the data strobe DS*, and waits for the mezzanine to acknowledge the data. The TDC then raises DS*, waits for the mezzanine to raise DK*, and finally raises AS* to indicate the end of the cycle.
If the cycle is a read, the TDC stops driving the AD bus, asserts "TDC ready", and waits for the mezzanine to provide the data. (Note that the "TDC ready" to "mezzanine data valid" delay can be increased by adding additional buffers in the Xilinx design.) The TDC then acknowledges the data and waits for the mezzanine to relinquish the AD bus. Finally, the TDC raises AS* to indicate the end of the then acknowledges the data and waits for the mezzanine to relinquish the AD bus. Finally, the TDC raises AS* to indicate the end of the cycle.
Fig 6. The parallel bus write protocol.
Fig. 7 The parallel bus read cycle protocol.
Fig. 8 The Mentor Schematic: CLBs = ~25 + 4n I/O Pins = 13 3-state Buffers = 8n 3-state Longlines = 8
Component Clearance Recommendations
Component placement on the mezzanine card must be done with care since the spacing on and around the card is very tight. Airflow considerations require that the components be chosen with as short a profile as possible. VME standards specify that the cards are on 0.8 inch centers. The allowed clearance between board components and the adjacent board region (its 0.8 inch area) is set at 50 mils. This stay clear region is defined for both the solder and component sides yielding a 100 mils clearance between boards. Fig. 9 below displays the allocation of the 0.8 inch space. The TDC/mezzanine card connector stack results in a separation of 12mm (0.472 inch) between the TDC and mezzanine card surfaces. The diagram assumes a 93 mil TDC board and a 62 mil mezzanine board. The 0.472 inch space between the boards is expected to house 0.15 inch of TDC components and similar height mezzanine card components with 0.172 inch of airflow space. Clearly, heat emitted in this area will be restricted.
Power and Cooling Considerations
The mezzanine card has numerous pins for power, 4 VCC lines on connector #1, 2 each on connectors #2 and #3. The limitation placed on these pins is 2 amps each. Connectors #2 and #3 each provide 2 pins for -5.2V with the same limitation on current. The tight spacing of the mezzanine and TDC cards constrains the power consumption of the mezzanine card more so than the current limitation of the input pins. Were one to try to carry away the power between the TDC and mezzanine card with airflow between the components completely filling the space except for a gap of 0.2 inch by 7 inch with 10oC difference between the component and air temperature, airflow of several tenths of a ft./sec is required per watt of dissipation. Clearly, this is a pessimistic calculation since it does not consider airflow on the back side of the two cards nor does it include any radiation heat loss. These effects together imply that, the power removed in watts ~ 3 x velocity of airflow in ft./sec for a 10oC differential in temperature between components and air. The above calculation is to be considered a rough estimate and better numbers are to be obtained as cards are tested.