November 6, 1997

Version 1

LOCOS -

a Local Control and Sum Board

M.Tecchio

1. Introduction

LOCOS is a 9U VME printed circuit board developed at University of Michigan as part of the Calorimeter Level 2 Trigger of the CDF II detector. It is intended to serve as a crate-wise control board in the cluster finding protocol, mediating between the board which contains the tower by tower energy information, or DCAS, and the calorimeter-wise control board, or CLIQUE. LOCOS is also designed to pass any cluster information, as they are found in the event, to the Level 2 decision board. A description of the Calorimeter L2 Trigger Architecture is contained in Section 2. Section 3 describes in details all of LOCOS functions: translation of control signals from CLIQUE to DCAS, in-crate seed selection and cluster energy sum, and transmission of cluster information to the Level 2 Processor. The board is also designed to read and write the VME signals running on the P1 and P2 backplanes for debugging purposes. The test version of the board is presently under fabrication.

2. Calorimeter L2 Trigger Architecture

The main task of the Level 2 Calorimetry Trigger is to sort out in clusters the digitized calorimeter energy sent by the Level 1 trigger board, or DIRAC, at each Level 1 Accept. For trigger purposes, the electromagnetic and the hadronic calorimeters are divided into 24h x 24f towers covering the central ( | h | < 1.1 ) and the forward ( 1.1 < | h | < 3.6) detectors,. The energy deposited by an event arrives from DIRAC as 10 bits ( 125 MeV LSB, 128 GeV Full Scale) of electromagnetic (EM) and 10 bits of hadronic (HAD) Et energy for each of the 576 trigger towers. We envision six Level 2 Calorimeter crates. Each crate will contain 12 DCAS boards and control the energy of a calorimeter wedge spanning over 24h x 4f trigger towers (see Sarah's "DCAS Cluster Finding Modules Diagram" in the CDF Home Page Upgrade DCAS Description area).

DCAS -Digital Cluster And Sum board- receives the energy from 8 h-adjacent trigger towers in the same f wedge and stores it in up to four L2 buffers following the TRACER directions. Once told by CLIQUE via LOCOS which of the four buffers has to be processed next, DCAS compares each tower energy with one of four sets of high and low thresholds to decide whether that tower is a seed or a shoulder for the current pass. The results of the comparison are transmitted to LOCOS which, if given by CLIQUE cluster-boss authority over the next cluster, picks the cluster starting seed. After the seed has been picked, DCAS performs the cluster expansion over all the neighboring shoulder towers and sums the energy of all the towers found to be part of the cluster.

DCAS operates under the surveillance of the LOCOS -LOcal COntrol and Sum - board. This board connects DCAS to the CLIQUE - CLuster Information QUEen - board, which acts as a master in orchestrating the cluster finding protocol for the entire event. There is one LOCOS board per crate, whence the name local. Each LOCOS is connected to the CLIST - Cluster LIST - board in the Level 2 Decision crate. CLIST acts as the calorimeter preprocessor board, collecting the cluster information from all six LOCOS boards and presenting it in a standard format to the Alpha Processor for the final L2 Accept decision.

The communication between LOCOS and DCAS is ensured by a custom-made J3 backplane to which all board are plugged via a 220-pin P3 connector. A list of the signals connected to LOCOS P3 pins is contained in Table 1. The signals that LOCOS receives and sends back to CLIQUE run on a 25-mil 50- conductor ribbon-cable connecting the CLIQUE front-panel to the front panel of the LOCOS Transition board. This board is located on the back of the calorimeter crate in the same slot where LOCOS sits and is plugged into the same J3 connector used by LOCOS. Its function is to route the control signals exchanged between LOCOS and CLIQUE from a 4-row 50-pin CHAMP connector on LOCOS_TRANS front-panel to the J3 connector pins in common with LOCOS. The only other connection of LOCOS to the external world consists of the cable carrying the cluster information to CLIST. At the time of this note, we are still evaluating two possible connections, once via a traditional 50-mil 20-conductor ribbon-cable from LOCOS to CLIST front-panels driven by a 28-bit Channel Link LVDS Transmitter, the other via an optical fiber or coaxial cable driven by a HOTLink Transmitter.

In parallel to the clusterfinding activity, cluster isolation sums are computed for the subset of passes intended for electron/photon identification. These are energy sums over 5 different clusters with a fixed number of towers around (and excluding) the seed tower. A set of six local control boards, one global control board and one preprocessor board are being developed in Argonne for calcuting these sums in time for the Level 2 Accept Decision.

3. LOCOS

The main task of LOCOS is to distribute to DCAS the control signals sent out by CLIQUE and send the information about the cluster position and cluster transverse energy Et to CLIST. A block diagram of LOCOS board is contained in Figure1. A detailed description of the L2 clustering protocol signals appearing there can be found Sarah's document /usr/phyusr/cdf_doc/clusterfing_signals_2.doc.

Table 1: LOCOS P3/J3 Pinout

3a. Control Signal Translation

The control signals sent from CLIQUE to LOCOS are meant to coordinate over the entire calorimeter the following cluster finding steps: selecting the L2 buffer

(CURR_B(1:0) ) and the threshold set (SEL_THR(1:0) ) to be processed next; orchestrating the beginning of a new event or of a new pass analysis (BUF_STRB, THR_STRB, START_PASS, PASS_DONE); delegating to one crate at the time the cluster-boss authority of picking the seed around which the cluster will be formed (SEED_REQ, CRATE_SEL); deciding when the cluster has finished its expansion (ERASE_CLUSTER); supervising the in-crate sums for the number of towers and total energy in the cluster (START_RIPPLE); and synchronizing the shipping of cluster information from the six different crates to the Cluster LIST board (CRSUM_SEND). Some signals are sent from LOCOS to CLIQUE. They signal that at least one seed has been found inside the crate (CRATE_HSD); that one seed has been selected by the crate with cluster-boss authority (SEED_SEL); that the crate is still working on the cluster-expansion (CRATE_ON); and that the in-crate cluster sums are done (CRSUM_DONE). These control signals arrive to and leave from LOCOS as differential LVDS signals. A set of National DS90CR30/31 transmitters/receivers transform them into single-ended TTL in-board signals as soon as they are detected on or are ready to be sent to the J3 backplane.

3b. Seed Selection, Cluster Expansion and In-Crate Energy Sum

LOCOS is designed to perform three main internal functions; the first is deciding which among the in-crate DCAS boards reporting the presence of a seed can proceed to select the tower around which to expand the cluster. Only the LOCOS with cluster-boss authority is allowed to delegate such authority to one of the 12 in-crate DCAS boards. Two reprogrammable PAL devices, operating in parallel to perform as a single one-step priority encoder, are used for such decision. Based on the status of the BRD_HSD(11:0) bits they produce the BRD_SEL(11:0) bits containing the selection decision and the local coordinates of the seed position in the 24x4 trigger tower submatrix. The VHDL code used to program the two PALs is contained in Appendix A.

The second LOCOS internal function is monitoring the status of the J3_PROPAGATING* line. This is an open collector signal common to all DCAS boards, which shows activity, in terms of 30-40 nsec pulses, as long as at least one DCAS is finding neighbor shoulder towers to add to the present cluster. An RC circuit with 15 nsec time constant is used to transform this chopped signal into a single pulse (CRATE_ON) which is sent to CLIQUE to signal the duration of the cluster spreading. CLIQUE, in response to a termination of cluster-spreading activity from all of the six LOCOS boards, sends out the ERASE_CLUSTER signal. At the arrival of this end-of-clustering signal, each DCAS board latches the energy of the towers involved in the current cluster to an adder and sets a mask to prevent them to be part of another cluster with the same pass number.

The last internal LOCOS function is the summing of the number of towers and total energy in the current cluster over the whole crate. The partial sums from the DCAS boards comes in the form of two daisy-chain sums from the six DCAS board on the left and the six DCAS on the right of LOCOS in the crate. The two daisy-chain sums are started by the START_RIPPLE command. Enough time is allowed for the sums to ripple through the daisy-chains and be computed inside LOCOS using a 500 nsec maximum 10-tap delay line controlled by an eight position DIP switch. The 13-bit energy sums (12 data bits plus one overflow bit) and 7-bit number of tower sums on LOCOS are done using 74F381 and 74F382 4-bit adders, cascaded via a 74F182 Look-Ahead Carry Chip. Only when their outputs are stable the CRSUM_DONE command is set.

3c. Cluster bit Transmission

At the end of the cluster expansion, 45 bits of information have to be sent from each LOCOS to the CLIST board as summarized in Table 2. These bits are sent from LOCOS front panel as differential signals. To minimize the number of cables and hence the size of the 6 receiving connectors that have to fit in the CLIST board front panel, we are testing two serial link solutions.

Table 2: Cluster Informatin bits

The first serial link mounted on the LOCOS test board is the 28-bit Channel Link. It can convert up to 28 TTL parallel signals into 4 pairs of LVDS (Low Voltage Differential Signal) lines and transmits them in parallel to a Phase Locked Clock running at a rate of 20 to 40 MHz. One pair of differential outputs is required for the clock lines, plus at least one extra GROUND line for a total of 11 lines minimum between the transmitter and the receiver chips. Using a traditional ribbon cable for connecting the transmitter to the receiver, low data rates and a maximum length of 30 ft are recommended. To detect possible transmission errors, an EDAC- Error Detection and Correction chip, has been added to the transmission path. This chip reads up to 32 input bits and produces 7 control bits which uniquely identify the bit input data. The control bits are sent together with the input bits and compared against the data received on the other side for possible errors in the transmission. The EDAC has the ability to detect both single and multiple bit errors and can be run in a mode to automatically correct single-bit error.

The Channel Link on LOCOS is clocked at 20 MHz via an on-board oscillator. The 45 bits of cluster information are divided into three groups of 15 bit each so that the input data plus the 7 control bits produced by the EDAC and 2 extra validation bits identifying which, if any, of the three groups of data are being sent at any given time, are presented at the Channel Link Inputs every 100 nsec. This corresponds to changing input bits only every other rising edge of the phase locked clock and it is dictated by the time required to produce or compare the EDAC control bits at both ends of the link. In the above scheme, the transmission time for the complete cluster information from LOCOS to CLIST is 300 nsec per cluster. The validation bits and the signals enabling the three group of 15 data bits into the Channel Link are produced by a state machine clocked at 10 MHz. The details of its implementation into a 22V10 PAL are presented in

Appendix B.

The second link solution foresees the use of the HOTLink chip. The HOTLink sends 8 parallel bits, at a maximum rate of 40MHz, using a single pair of differential signals. The 8 bits are internally encoded into 10 bits and sent out as a serial stream. The receiver recovers the timing information using a PLL Clock Synchronizer, deserializes the differential signals, decodes and checks them for transmission errors. The differential signals can be sent either via coaxial cable or, with the addition of an optical transmitter, via optical fiber. The HOTLink Link has been found to be very robust against transmission errors for coaxial cable connections up to 75 ft and optical fiber connection up to 400 ft. This last solution is particularly attractive for his immunity to environmental sources of noise. The same 20 MHz on-board oscillator used for the Channel-Link, can be used drive the HOTLink Transmitter Clock via a two-way slide switch. The 45-bit of cluster information is divided into six groups of 8 bits each. The HOTLink transmitter sends out continuously zeroes unless explicitly enabled. For our applications, the enable is given the logical OR of the control signals used to latch the six group of valid data onto the HOTLink inputs bus. A state machine implemented inside a 22V10 PAL (see Appendix B for details) produces the six consecutive latching signals at a rate of 20 MHz, for a total transmitting time of 300 nsec, as in the Channel-Link solution.

3d. VME Interface

At present, LOCOS is not designed to sent any information into the CDF Data Acquisition Stream. Nevertheless, the circuitry for a full VME interface has been added to the board for testing and debugging purposes. The details of the VME Address Space implemented in the test version of the board are contained in a separate document. The interface has been designed to allow the following actions:

• soft VME reset
• programmable running mode. One can choose to run LOCOS in one of the five following running conditions: simulate all signals from CLIQUE, simulate all signals from DCAS, simulate all signals intended for CLIST, simulate all internally produced signals intended for DCAS and simulate all internally produced signals intended for CLIQUE.
• simulate/test all control signals received from CLIQUE. This is done with set and clear commands which drive the inputs of dedicated JK flip-flop so that the rising and the falling edge of each control signal can be controlled via VME.
• simulate/test the seed selection protocol by writing predefined bit patterns to the PALs inputs and/or reading the resulting output bits.
• simulate/test the inputs/output of the daisy-chain sum circuitry.
• simulate/test all the cluster information sent to CLIST via either transmission paths.

A template of the circuitry used to implement the simulation or test functions described above is contained in Fig.2

Figure 2. Template of the LOCOS circuitry used for writing/reading to a local data bus for simulation/testing purposes. Shown here are two local busses, BUS_A and BUS_B, connected by some Internal Circuitry (double-cross box). BUS_A is read from the J3 Backplane and BUS_B is sent to the J3 Backplane. The SEL_MODE_A* and SEL_MODE_B* signals are set by the running mode chosen for LOCOS. They allows to select between "real" data on the bus or data simulated by a VME Write cycle, enabled by the corresponding WR_BUS_A and WR_BUS_B signals. Both real or simulated data can be read via VME setting the appropriate RD_BUS_A or READ_BUS_B signals.

APPENDIX A

LOCOS contains two 22V10 PALs (referenced as LSB8_PAL and LSBENC_PAL) dedicated to the selection of only one DCAS board among the ones which report having a seed. They work in parallel so to implement an one-stage priority encoding of the information contained in the BRD_HSD(11:0) bus into the BRS_SEL(11:0) bus (i.e. the input bus contains as many 1 bits as there are DCAS with at least one seed while the output bus contains only one 1 bit in correspondence to the LSB board which contains a seed).The first PAL - LSB8_PAL - reads the 8 lowest significant bits of the BRD_HSD bus and encodes it into the 8 lowest significant bits of BRD_SEL, while the second PAL - LSBENC_PAL - reads all 12 bits of BRD_HSD and does the encoding of the 4 most significant bits of BRD_SEL. The LSBENC_PAL sends out four more bits which contains the position of the seed in the 24hx4f trigger tower submatrix controlled by the crate; 2 bits for the f position and 2 bits for the 2 most significant bits of the h position (the remaining 3 being set by DCAS when one among the 8 towers controlled by the board is found to have the seed). The two PALs have also two common control inputs: an ENABLE input directly connected to the CRATE_SEL signal which enable the seed selection only for the LOCOS with cluster-boss authority

and an ERASE* input which zeroes all the output whenever a end-of-cluster expansion signal, ERASE_CLUSTER, is detected or when the board is reset.

In the following the VHDL code used to program the two PALs is presented, together with the PALs pinout.

LSB8.VDHL

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY seed_board_8 IS PORT (

-- BRD_HSD(7:0) => any board with seed

brd_hsd : IN std_logic_vector(7 DOWNTO 0);

-- enable => signals valid inputs

en : IN std_logic;

-- erase => board reset + end of cluster reset

erase : IN std_logic;

-- BRD_SEL(7:0) => LSB board with seed

brd_sel : OUT std_logic_vector(7 DOWNTO 0)

);

END seed_board_8;

ARCHITECTURE lsb_arch OF seed_board_8 IS

BEGIN

lsb: PROCESS(en,erase)

BEGIN

-- take care of valid "enable" and "erase" signals

IF en = '1' THEN

IF erase = '1' THEN

brd_sel(0) <= brd_hsd(0);

-- select lsb inputs, ignore status of others

brd_sel(1) <= NOT brd_hsd(0) AND brd_hsd(1);

brd_sel(2) <= NOT brd_hsd(0) AND NOT brd_hsd(1) AND

brd_hsd(2);

brd_sel(3) <= NOT brd_hsd(0) AND NOT brd_hsd(1) AND

NOT brd_hsd(2) AND brd_hsd(3);

brd_sel(4) <= NOT brd_hsd(0) AND NOT brd_hsd(1) AND

NOT brd_hsd(2) AND NOT brd_hsd(3) AND

brd_hsd(4);

brd_sel(5) <= NOT brd_hsd(0) AND NOT brd_hsd(1) AND

NOT brd_hsd(2) AND NOT brd_hsd(3) AND

NOT brd_hsd(4) AND brd_hsd(5);

brd_sel(6) <= NOT brd_hsd(0) AND NOT brd_hsd(1) AND

NOT brd_hsd(2) AND NOT brd_hsd(3) AND

NOT brd_hsd(4) AND NOT brd_hsd(5) AND

brd_hsd(6);

brd_sel(7) <= NOT brd_hsd(0) AND NOT brd_hsd(1) AND

NOT brd_hsd(2) AND NOT brd_hsd(3) AND

NOT brd_hsd(4) AND NOT brd_hsd(5) AND

NOT brd_hsd(6) AND brd_hsd(7);

ELSE

-- when "erase" is present, send out no selected board

brd_sel <= "00000000";

END IF;

ELSE

-- when invalid inputs, send out no selected board

brd_sel <= "00000000";

END IF;

END PROCESS lsb;

END lsb_arch;

LSB8.PINOUT

LSB8.SIMULATION

LSBENC.VDHL

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY seed_board_all IS PORT (

-- BRD_HSD(11:0) => any board with seed

brd_hsd : IN std_logic_vector(11 DOWNTO 0);

-- enable => signals valid inputs

en : IN std_logic;

-- erase => signals board reset + end of cluster reset

erase : IN std_logic;

-- BRD_SEL(11:8) => top 4 LSB board with seed

brd_sel : OUT std_logic_vector(11 DOWNTO 8);

-- SEED POS: board number encoding into (eta,phi) coord.

-- NB: board relabelling is needed to go from

-- DCAS label COORD label

-- ^ ^

-- phi=3 | 9 10 11 phi=3 | 3 7 11

-- phi=2 | 6 7 8 phi=2 | 2 6 10

-- phi=1 | 3 4 5 phi=1 | 1 5 9

-- phi=0 | 0 1 2 phi=0 | 0 4 8

-- ----------------------> ----------------------->

-- eta = 0 to 24 eta = 0-7 8-15 16-23

seed_phi : OUT std_logic_vector(1 DOWNTO 0);

seed_eta : OUT std_logic_vector(3 DOWNTO 2)

);

END seed_board_all;

ARCHITECTURE lsb_enc OF seed_board_all IS

-- product terms needed to implement 74F148 logic

-- (8 to 3 priority encoded, see National datasheet)

-- Actually we need to calculate product terms for

-- two 74F148s cascaded together since we are dealing

-- with 12 inputs (last 4 inputs of second encoder

-- will be fixed to GND)

SIGNAL p_high: std_logic_vector(12 DOWNTO 1);

SIGNAL a_high: std_logic_vector(2 DOWNTO 0);

SIGNAL ei_high, eo_high, gs_high: std_logic;

SIGNAL p_low: std_logic_vector(12 DOWNTO 1);

SIGNAL a_low: std_logic_vector(2 DOWNTO 0);

SIGNAL ei_low, eo_low, gs_low: std_logic;

-- 74F148 works in negative logic => to apply

-- to positive logic signals, such as BRD_HSD

-- and BRD_SEL, one needs:

-- 1) invert input signals

-- ( brdstar = NOT brd_hsd)

-- 2) invert order of bit connections so that

-- brdstar(0) = I(7) of MSB 74F148

-- brdstar(1) = I(6) " "

-- ............

-- brdstar(7) = I(0) " "

-- brdstar(8) = I(7) of LSB 74F148

-- ............

-- brdstar(11)= I(4) " "

-- brdstar(12 to 15) = NOT '0'

SIGNAL brdstar: std_logic_vector(15 DOWNTO 0);

SIGNAL brdtemp: std_logic_vector(15 DOWNTO 12);

-- do coordinate relabelling AFTER lsb board has been selected

SIGNAL coord0, coord1, coord2, coord3 : std_logic;

SIGNAL brdhsd: std_logic_vector(3 DOWNTO 0);

SIGNAL brdsel: std_logic_vector(3 DOWNTO 0);

BEGIN

-- tie four highest bits to ground

brdtemp(12) <= '0';

brdtemp(13) <= '0';

brdtemp(14) <= '0';

brdtemp(15) <= '0';

-- do signal inversion

brdstar <= NOT brdtemp & NOT brd_hsd;

-- calculate 74148s internal products: Enables and Group Signals

ei_high <= '0';

eo_high <= NOT( brdstar(0) AND brdstar(1) AND brdstar(2) AND

brdstar(3) AND brdstar(4) AND brdstar(5) AND

brdstar(6) AND brdstar(7) AND NOT ei_high);

gs_high <= NOT( eo_high AND NOT ei_high);

ei_low <= eo_high; -- enable connectionn for 16 bit expansion

eo_low <= NOT( brdstar(8) AND brdstar(9) AND brdstar(10) AND

brdstar(11) AND brdstar(12) AND brdstar(13) AND

brdstar(14) AND brdstar(15) AND NOT ei_low);

gs_low <= NOT( eo_low AND NOT ei_low);

-- intermediate product terms: 12 ANDs

p_high(1) <= brdstar(5) AND NOT brdstar(6) AND brdstar(3) AND

brdstar(1) AND NOT ei_high;

p_high(2) <= brdstar(3) AND NOT brdstar(4) AND brdstar(2) AND

brdstar(1) AND NOT ei_high;

p_high(3) <= brdstar(1) AND NOT brdstar(2) AND NOT ei_high;

p_high(4) <= NOT brdstar(0) AND NOT ei_high;

p_high(5) <= brdstar(2) AND brdstar(3) AND NOT brdstar(5) AND

NOT ei_high;

p_high(6) <= p_high(2);

p_high(7) <= NOT brdstar(1) AND NOT ei_high;

p_high(8) <= p_high(4);

p_high(9) <= NOT brdstar(3) AND NOT ei_high;

p_high(10)<= p_high(3);

p_high(11)<= p_high(7);

p_high(12)<= p_high(4);

p_low(1) <= brdstar(13) AND NOT brdstar(14) AND brdstar(11) AND

brdstar(9) AND NOT ei_low;

p_low(2) <= brdstar(11) AND NOT brdstar(12) AND brdstar(10) AND

brdstar(9) AND NOT ei_low;

p_low(3) <= brdstar(9) AND NOT brdstar(10) AND NOT ei_low;

p_low(4) <= NOT brdstar(8) AND NOT ei_low;

p_low(5) <= brdstar(10) AND brdstar(11) AND NOT brdstar(13) AND

NOT ei_low;

p_low(6) <= p_low(2);

p_low(7) <= NOT brdstar(9) AND NOT ei_low;

p_low(8) <= p_low(4);

p_low(9) <= NOT brdstar(11) AND NOT ei_low;

p_low(10)<= p_low(3);

p_low(11)<= p_low(7);

p_low(12)<= p_low(4);

-- final product terms: 3 NORs

a_high(0) <= NOT(p_high(1) OR p_high(2) OR p_high(3) OR p_high(4));

a_high(1) <= NOT(p_high(5) OR p_high(6) OR p_high(7) OR p_high(8));

a_high(2) <= NOT(p_high(9) OR p_high(10) OR p_high(11) OR p_high(12));

a_low(0) <= NOT(p_low(1) OR p_low(2) OR p_low(3) OR p_low(4));

a_low(1) <= NOT(p_low(5) OR p_low(6) OR p_low(7) OR p_low(8));

a_low(2) <= NOT(p_low(9) OR p_low(10) OR p_low(11) OR p_low(12));

-- lsb BOARD in DCAS label using info from both 148s

coord0 <= a_high(0) AND a_low(0);

coord1 <= a_high(1) AND a_low(1);

coord2 <= a_high(2) AND a_low(2);

coord3 <= gs_high;

-- do relabelling

brdhsd <= coord3 & coord2 & coord1 & coord0;

WITH brdhsd SELECT

brdsel <= "0000" WHEN "0000",

"0001" WHEN "0011",

"0010" WHEN "0110",

"0011" WHEN "1001",

"0100" WHEN "0001",

"0101" WHEN "0100",

"0110" WHEN "0111",

"0111" WHEN "1010",

"1000" WHEN "0010",

"1001" WHEN "0101",

"1010" WHEN "1000",

"1011" WHEN "1011",

"1111" WHEN OTHERS;

-- take care of PAL "enable" and "erase" signals

lsb: PROCESS(en,erase)

BEGIN

IF en = '1' THEN

IF erase = '1' THEN

-- LSB encoding for 4 highest bits ( lowest 8

-- bits done in another PAL)

brd_sel(8) <= NOT brd_hsd(0) AND NOT brd_hsd(1) AND

NOT brd_hsd(2) AND NOT brd_hsd(3) AND

NOT brd_hsd(4) AND NOT brd_hsd(5) AND

NOT brd_hsd(6) AND NOT brd_hsd(7) AND

brd_hsd(8);

brd_sel(9) <= NOT brd_hsd(0) AND NOT brd_hsd(1) AND

NOT brd_hsd(2) AND NOT brd_hsd(3) AND

NOT brd_hsd(4) AND NOT brd_hsd(5) AND

NOT brd_hsd(6) AND NOT brd_hsd(7) AND

NOT brd_hsd(8) AND brd_hsd(9);

brd_sel(10) <= NOT brd_hsd(0) AND NOT brd_hsd(1) AND

NOT brd_hsd(2) AND NOT brd_hsd(3) AND

NOT brd_hsd(4) AND NOT brd_hsd(5) AND

NOT brd_hsd(6) AND NOT brd_hsd(7) AND

NOT brd_hsd(8) AND NOT brd_hsd(9) AND

brd_hsd(10);

brd_sel(11) <= NOT brd_hsd(0) AND NOT brd_hsd(1) AND

NOT brd_hsd(2) AND NOT brd_hsd(3) AND

NOT brd_hsd(4) AND NOT brd_hsd(5) AND

NOT brd_hsd(7) AND NOT brd_hsd(7) AND

NOT brd_hsd(8) AND NOT brd_hsd(9) AND

NOT brd_hsd(10) AND brd_hsd(11);

-- final seed coordinates encoding using relabelled boards

seed_phi(0) <= brdsel(0);

seed_phi(1) <= brdsel(1);

seed_eta(2) <= brdsel(2);

seed_eta(3) <= brdsel(3);

ELSE

-- when ERASE condition appears (board reset or end-of-cluster)...

brd_sel <= "0000"; -- no BOARD selected

seed_phi <= "11"; -- invalid seed coordinate to

seed_eta <= "11"; -- distinguish from case in which

-- BOARD 0 is selected

brd_sel <= "0000";

seed_phi <= "11";

seed_eta <= "11";

END IF;

ELSE

-- when PAL is disabled (no valid info at inputs).....

brd_sel <= "0000"; -- no BOARD selected

seed_phi <= "11"; -- invalid seed coordinate to

seed_eta <= "11"; -- distinguish from case in which

-- BOARD 0 is selected

END IF;

END PROCESS lsb;

END lsb_enc;

LSBENC_PAL PINOUT

APPENDIX B

The two serial links connecting LOCOS to CLIST require to clock out the 45 bits of cluster information synchronously with the link clock for a number of consecutive cycles varying from 3 for the Channel Link, at a rate of 10MHz, to 6 for the HOTLink, at a rate of 20MHz.

Different validation schemes have been implemented for the two data streams so that the the receiver chip on the CLIST board can recognize when valid data are being sent.

In the Channel Link scenario, the validation bits are an extra pair of bits sent in parallel to the data stream, whose value is different from "00" only when valid cluster information is being transmitted and changes from "01" to "11" as the three group of 15 data bits are presented to the Channel Link inputs. Both the validation bits and the enable inputs to the latches holding the three groups of 15 data bits are produced by a state machine programmed inside a 22V10 PAL referenced as CLINK_PAL.

In the HOTLink solution, the 45 bits of data are divided into 6 group of 8 bits each. The 8-bits sent by HOTLink are always zeroes unless the chip is explicitly enabled. When a cluster is ready to be sent, the first bit of the first 8-bit of valid data is tied high to signal the receiver chip that the six consecutive cycles of valid data are coming. To track down possible transmission errors or hiccups, also the first bit of the third and fifth group of 8 bits are tied high. The enable inputs to the latches holding the six groups of 8 data bits are produced by a second state machine programmed inside a 22V10 PAL referenced as HLINK_PAL.

The VHDL programs for the state machines and the PAL pinouts are given in the following. The two PALS are enabled one at the time by a two-way slide switch LINK_SW. The common enable line is turned on by the leading edge of the CRSUM_SEND signal and turned off by either a board reset or one of the two state machines reaching its maximum count. The combination of two three signals is also used to reset the state machines to their initial count value of zero.

CLINK.VDHL

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE work.numeric_std.ALL;

ENTITY clink_pal IS PORT (

-- inputs: clock, reset (negative logic) and enable

clock, enable, reset : IN std_logic;

-- 16-bit latch output enables (negative logic)

oe1, oe2, oe3, oe4 : BUFFER std_logic;

-- control bits for the channel-link valid data

cntrl: OUT unsigned(1 DOWNTO 0)

);

END clink_pal;

ARCHITECTURE clink_controller OF clink_pal IS

-- define state machine states

TYPE states IS (idle,en_1,en_2,en_3,en_4);

SIGNAL fsm_register : states;

BEGIN

-- State machine with synchronous reset and asynchronous enable.

-- It generates the 16-bit latch output enables to the CLINK data bus.

oe_enable: PROCESS (clock,reset)

BEGIN

IF clock'EVENT AND clock = '1' THEN

IF reset = '0' THEN

cntrl <= "00";

fsm_register <= idle;

ELSE

IF (enable = '1') THEN

cntrl <= cntrl + 1;

ELSE

cntrl <= "00";

END IF;

CASE fsm_register IS

WHEN idle => IF (enable = '1') THEN

fsm_register <= en_1;

ELSE

fsm_register <= idle;

END IF;

WHEN en_1 => IF (enable = '1') THEN

fsm_register <= en_2;

ELSE

fsm_register <= en_1;

END IF;

WHEN en_2 => IF (enable = '1') THEN

fsm_register <= en_3;

ELSE

fsm_register <= en_2;

END IF;

WHEN en_3 => IF (enable = '1') THEN

fsm_register <= en_4;

ELSE

fsm_register <= en_3;

END IF;

WHEN en_4 => IF (enable = '1') THEN

fsm_register <= idle;

ELSE

fsm_register <= en_4;

END IF;

WHEN OTHERS => fsm_register <= idle;

END CASE;

END IF;

END IF;

END PROCESS oe_enable;

oe1 <= '0' WHEN ( fsm_register = en_1 ) ELSE '1';

oe2 <= '0' WHEN ( fsm_register = en_2 ) ELSE '1';

oe3 <= '0' WHEN ( fsm_register = en_3 ) ELSE '1';

oe4 <= '0' WHEN ( fsm_register = en_4 ) ELSE '1';

END clink_controller;

CLINK_PAL PINOUT

HLINK.VDHL

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY hlink_pal IS PORT (

-- following are inputs;

-- clock, enable (positive logic), reset (negative logic)

clock, enable, reset : IN std_logic;

-- now the 8-bit latch output enables (negative logic)

oe1, oe2, oe3, oe4, oe5, oe6, oe7: OUT std_logic

);

END hlink_pal;

ARCHITECTURE hlink_controller OF hlink_pal IS

-- define state machine states

TYPE states IS (idle,en_1,en_2,en_3,en_4,en_5,en_6,en_7);

SIGNAL fsm_register : states;

BEGIN

-- state machine with synchronous reset and asynchronous enable

-- It generates the 8-bit latch output enables to the HOTLINK data bus.

oe_enable: PROCESS (clock,reset)

BEGIN

IF clock'EVENT AND clock = '1' THEN

IF reset = '0' THEN

fsm_register <= idle;

ELSE

CASE fsm_register IS

WHEN idle => IF (enable = '1') THEN

fsm_register <= en_1;

ELSE

fsm_register <= idle;

END IF;

WHEN en_1 => IF (enable = '1') THEN

fsm_register <= en_2;

ELSE

fsm_register <= en_1;

END IF;

WHEN en_2 => IF (enable = '1') THEN

fsm_register <= en_3;

ELSE

fsm_register <= en_2;

END IF;

WHEN en_3=> IF (enable = '1') THEN

fsm_register <= en_4;

ELSE

fsm_register <= en_3;

END IF;

WHEN en_4 => IF (enable = '1') THEN

fsm_register <= en_5;

ELSE

fsm_register <= en_4;

END IF;

WHEN en_5 => IF (enable = '1') THEN

fsm_register <= en_6;

ELSE

fsm_register <= en_5;

END IF;

WHEN en_6 => IF (enable = '1') THEN

fsm_register <= en_7;

ELSE

fsm_register <= en_6;

END IF;

WHEN en_7 => IF (enable = '1') THEN

fsm_register <= idle;

ELSE

fsm_register <= en_7;

END IF;

WHEN OTHERS => fsm_register <= idle;

END CASE;

END IF;

END IF;

END PROCESS oe_enable;

oe1 <= '0' WHEN ( fsm_register = en_1 ) ELSE '1';

oe2 <= '0' WHEN ( fsm_register = en_2 ) ELSE '1';

oe3 <= '0' WHEN ( fsm_register = en_3 ) ELSE '1';

oe4 <= '0' WHEN ( fsm_register = en_4 ) ELSE '1';

oe5 <= '0' WHEN ( fsm_register = en_5 ) ELSE '1';

oe6 <= '0' WHEN ( fsm_register = en_6 ) ELSE '1';

oe7 <= '0' WHEN ( fsm_register = en_7 ) ELSE '1';

END hlink_controller;

HLINK.PAL PINOUT