Designing Custom IC's

C. Murphy

August, 1997

To design custom IC's using the Cascade silicon compiler, the first task is to create your design in verilog. The compiler, epoch, has a parts library on line that lists the various parts and how the nets are connected. We also have a collection of epoch and verilog manuals in pink binders in the e-shop library. Your verilog files should be put into a directory called verilog under the project directory. It is recommended that you specify the pin numbering that you want for all pins in on the chip.

To set up your account to use the compiler, you will need to add the following lines to your .cshrc file.

setenv CASCADE /usr/caen/cascade.beta

set path = ( $CASCADE/bin $path )

Now you can start the compiler. First go to the directory where you want to have your design. Chip designs are currently in /nfs/voyager/l/projects/chip_projects. Just type epoch, and the compiler window should come up. You will now need to set the project and ruleset. Go to the Project menu and select New. Type in the path to the project directory and an ID for the project. I usually just put in my initials. Now go to the Project menu again and select ruleset. The available rulesets will be listed and you can select one. The HP26G rules are for the .8 micron HP CMOS process. The HP14B rules are for the .5 micron HP process.

To compile your chip, you first need to compile the verilog input file and "netlist" it. If you don't want the compiler to randomly assign the pins on your chip, before doing that you will need to select a package under Physical Design>Parameters menu. This will bring up a list of packages to chose from. Then, under the Input menu, select Verilog Compile. A window pops up that lists all of the .v files in your verilog directory. Select the top level file and select "Run Netlist Input". Leave all other values the defaults. This will compile your verilog and tell you if there are any errors. If the verilog compiles successfully, the program goes on to netlist your files. For further explanation on anything discussed in this document, please see the Epoch manuals in the library- they describe the entire design process in detail.

Once the design is successfully netlisted, you will need to setup some parameters before you go on to the silicon compiler. Under the Physical Design>Parameters menu there are four items, timing, power, std cell routing, and packaging. You will need to go through these and set up the relevant items for your design. See the attached memo and the manuals for more details.

Now you can run the compiler. There are two options, you can go through the steps one at a time- or you can run it automatically and it should take care of everything. If you run it through one step at a time, you place the core, route the core, and buffer size the core. Finally you place and route the full chip. The Floorplanning option is for manual adjustment of the placement. You can also put a guard ring around your core if you wish.

Once you have a fully compiled chip, you will need to write out the verilog in a format that lets you simulate the chip with all extracted RC delays. First you will need to set up the simulation parameters under the Simulation menu. You will actually need to set them up for the minimum setting, then write out the files, set them up for the nominal, write out the files, etc.. See attached memo. The output from this should be six files- a chip_min.v, chip_min.sdf, chip_nom.v, chip_nom.sdf, etc.. The simulations are run on the .v file and there is a switch for the simulator to include the delays specified in the .sdf files.

In conjunction with simulating the final design, you will also need to run DRC and LVS checks on your chip. This needs to be done in Mentor's IC station, so you will first have to write out your design in GDSII and SPICE formats. For the spice output, don't size the transistors, put the NMOS and PMOS transistors as typical, and don't change any other of the default settings. For the GDSII output, make sure you select well merging- you can leave the other settings at the defaults. The output files will be put in two separate directories (spice and gds) under a directory in your design area named for the ruleset. (e.g. chip_projects/dat_phasing/hp26B/gds)

The DRC and LVS checks are run in Mentor- so double click on ic from design manager. In the window that comes up, there is a list of menu items down the right column. Click on IC link and select GDSII as the source format and ICGraph as the destination. You will get another window in which to type the path to the source GDS file and the path for the mentor parts. I usually create a directory under my design called mentor for this purpose. You can leave the options file blank. Once this completes successfully, you can select Cell>Open and navigate to the directory you supplied as the destination. There should be many files there, including one called "chip" and another called "chip_core". I run the DRC and LVS on the chip core- select this and click OK. The core should pop up in an edit window. Next go to File>Process>Set Cell Process.. and navigate to the mentor process file for your ruleset. For HP26G this file is in /nfs/voyager/l4/users/jmann/muon_tdc/mentor_parts/HP26G_proc. The cell should now change color schemes. Next select on the right side menu, ICrules>Load Rules. Load in the text DRC rules for your process, for HP26G this file is /nfs/voyager/l4/users/jmann/

muon_tdc/mentor_parts/drc_rules_hp26G. Now select Check and OK the box that appears at the bottom of the screen. You should look at the session transcript window, it will go through all of the rules one by one and list the number of "results". Each result is a violation of the rule and needs to be fixed. On the right menu, under Set Scan to, select First and then Next to scroll through all the violations. If you have a large number of results, it may be one problem in a sub cell that is used a number of times. You can look at the rules file for a hint on what rule is being violated. There is a binder in John Mann's office that has the correct rule spacing. If you do need to go in and manually edit the chip, you will have to write out the edited GDSII file.

To run LVS, you will first need to go through the spice file and edit out all capacitors. These are the lines that begin with C and a number. Now, back in ic with the cell loaded, process set, and rules loaded in- click on the right menu item labeled ICtrace(M). The menu that comes up has LVS, click on this and in the window that pops up, navigate to the source file- this is the edited spice output. You will need to know the subcircuit name and put this in the Subckt box. If you look at the beginning of the spice file, it should list the Cell name and what the subcircuit name is (e.g. Cell: t174s0 = CKT2 so the Subckt name is CKT2). Leave all of the other settings at their defaults and click OK. Check the transcript to make sure that LVS completed successfully.

Now that both DRC and LVS have been passed successfully (one hopes!) it's time to get ready to submit the design to MOSIS. To do this, you will need to uuencode the GDSII file. You should name the output file something like chip.uugds. See the man page for uuencode for details on using the command. Once that is finished, you'll need to run the program checksum on the file to get two numbers that Mosis uses to make sure the file transmitted successfully. There is a copy of the program in /nfs/voyager/l/mgc. Once you have the uuendcoded file and the two checksum numbers, you only need the purchase order number and you can submit your chip.

MOSIS has an automated e-mail system that is used to submit designs for fabrication. It works very well and you can see the MOSIS user manual for more details. I have found the easiest way to get the file to them is to put it in the anonymous ftp area (see Bob Ball for more info) and then you send the IP address, username, and password in the submission e-mail message and MOSIS automatically picks up the file. I have included all of the submission and response e-mails from MOSIS for the data phasing chip as an attachment to this file.